The creation of complex integrated circuits and semiconductor devices can be a very expensive undertaking given the large number of hours of sophisticated engineering talent involved in designing such devices. Additionally, integrated circuits can include read only memories and/or EEPROMs into which software, in the form of firmware, is encoded. Additionally, integrated circuits are often used in applications involving the encryption of information, and therefore in order to keep such information confidential, it can be desirable to keep such devices from being reverse engineered. Thus, there can be a variety of reasons for protecting integrated circuits and other semiconductor devices from being reverse engineered.
In order to keep the reverse engineer at bay, different techniques are known in the art to make integrated circuits more difficult to reverse engineer. One technique is to make the connections between transistors difficult to determine forcing the reverse engineer to carefully analyze each transistor (in particular each CMOS transistor pair for CMOS devices). Bit camouflaging the connections between transistors, the reverse engineer is unable to use automatic circuit and pattern recognition techniques in order to reverse engineer an integrated circuit. Since integrated circuits can have hundreds of thousands or even millions of transistors, forcing the reverse engineer to carefully analyze each transistor in a device can effectively frustrate the reverse engineer's ability to reverse engineer the device successfully.
The prior art techniques mentioned above, if successful, will force the reverse engineer to study the metal connections in an attempt to figure out the boundaries of standard circuits and their function. For example, gate connections may utilize the polysilicon layer (typically the first polysilicon layer in a process having two or more polysilicon layers) and the reverse engineer, knowing that such gate contacts are typically the input to transistors and hence to a standard circuit, would look for these contacts. Also, the source and drain contacts are made to the substrate via metal interconnect. One way in which the reverse engineer might work would be to look for cell boundaries by means of looking for silicon-to-gate poly metal lines as these suggest the possibilities for contacts between the output (the drain contact) from one transistor cell into the input (the gate contact) of a next transistor cell. If this can be done, the reverse engineer can define cell boundaries by these silicon-gate poly lines. Then by noting the cell boundaries, the reverse engineer can find the cell characteristics (for example, size and number of transistors) and from this make reasonable assumptions as to the cell's function. This information can then be stored in a database for automatic classification of other similar cells.
It is an object of this invention to make reverse engineering even more difficult and, in particular, to force the reverse engineer to study the possible silicon-to-gate poly lines very carefully, to see if they are in fact real. It is believed that this will make the reverse engineer's efforts all the more difficult by making it very time consuming in order to reverse engineer a chip employing the present invention and perhaps making it exceedingly impractical, if not impossible, to reverse engineer a chip employing the present invention.
The Inventors named herein have previously filed Patent Applications and have received Patents relating to the camouflage of integrated circuit devices in order to make it more difficult to reverse engineer them as discussed above. The present invention can often be used harmoniously with the techniques disclosed in these prior United States Patents to further confuse the reverse engineer.
In modern semiconductor manufacturing processes, particularly where the feature size is less than 0.5 micrometers, a silicide layer is typically used to improve conductivity. FIG. 1 is a plan view of a semiconductor device. FIGS. 1A, 1B and 1C are cross-sectional views of the semiconductor device shown in plan view in FIG. 1. A typical drain or source contact is shown in FIG. 1A, while a typical gate contact is shown in FIG. 1B. The drain, source and gate regions are formed on a semiconductor substrate, such as silicon substrate 10, and have active regions 12, 16, 18, as shown in FIG. 1C, formed therein, typically by implantation of a suitable dopant. Field oxide (FOX) 20 is used to help isolate one semiconductor device from another, in the usual fashion. The drain contact structure, as shown in FIG. 1A, has a conventional silicide layer 26-1 formed over its active region 18. A refractive metal contact 30 and plug 31 combination is formed on the silicide layer 26-1. Silicide layer 26-1 provides a surface for a refractive metal gate contact 30 and plug 31 combination, the metal contact frequently including a plug of refractive metal 31 which extends through an opening in a dielectric layer 29, which may be deposited SiO2. The refractive metal gate contact 30 and metal plug 31 combination makes contact with the silicide layer 26-1. The source structure is similar to the drain structure depicted in FIG. 1A, where the active region 18 is replaced by active region 16.
The gate structure, as shown in FIG. 1B, has a relatively thin gate oxide layer 22 which is covered by a layer of polysilicon 24-1, which in turn is covered by a silicide layer 26-1 (suicide layer 26-1 is traditionally referred to as a “salicide” layer when used with a polysilicon layer 24-1 as is the case here) Silicide layer 26-1 provides a surface for a refractive metail gale contact 30 the metal contact frequently including a plug of refractive metal 31 which extends through an opening in a dielectric layer 29, which may be deposited SiO2. The metal plug 31 makes contact with the silicide layer 26-1.
FIG. 1C is a cross-sectional view through the active areas 16, 18 and gate area 12 of a semiconductor device. The sidewall spacers 21 provide for the separation of the gate area 12 and active regions 16, 18 during processing. The remaining details of FIG. 1C are the same as those found in FIGS. 1A and 1B. Those skilled in the art will appreciate other fabrication details are omitted from the drawings since their use is well known in the art.
It is also common in the prior art to use a double-polysilicon CMOS fabrication process. Such a process is currently used by many commercial IC chip manufacturers, especially smart card chip manufacturers. The double-polysilicon (or simply double poly) process can be used to make a variety of devices, including CMOS transistor pairs, floating gate structures and even bipolar transistors. See, for example, U.S. Pat. No. 4,784,966 to Chen. A double-polysilicon CMOS process also supports the manufacture of EEPROMs, which are commonly used in applications such as smart card chips and the like.